1. Technical Field
The present disclosure relates to a substrate for packaging a semiconductor device, and to a conductive post of a substrate including a first portion with a first width and a second portion with a second width. The first portion and the second portion of the conductive post are exposed by a dielectric layer and the second width is greater than the first width.
2. Description of the Related Art
In some semiconductor device packages, for example, a package on package (PoP) structure, an upper substrate is stacked on a lower substrate. Solder balls may be used to connect the upper substrate to the lower substrate to form the semiconductor device package. However, it may be challenging to control a size/dimension of the solder balls and this may adversely affect assembly of the upper substrate and the lower substrate. Moreover, a width and a pitch of the solder balls may be greater than desired.
Copper (Cu) pillars, which can have relatively better uniformity in height and relatively smaller width and pitch, may be used to replace the solder balls between the upper substrate and the lower substrate. However, as technologies progress, semiconductor device packages are shrinking, and a height of Cu pillars and a corresponding manufacturing process may still cause issues.